74LS21 DUAL 4-INPUT AND GATE in Pakistan

This circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change together when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is held high. The counter is fully programmable; that is, each output may be preset to either level by entering the desired data at the inputs while the load input is low. The output will change independently of the count pulses.

The 74LS138 is a 3:8 Decoder IC that is commonly used in decoding or de-multiplexing circuits for memory decoding or data routing purposes. It is designed for high-speed operations and has three enable pins to make it easier to cascade with other ICs. The device decodes 1-of-8 lines, set by x3 binary select inputs & three enable inputs. The LS138 can be used as an 8- output demultiplexer by using one active LOW Enable input as data input & the other Enable inputs as strobes. The IC has an operating voltage from 1.0V to 5.5V with a low power consumption of 32mW. The propagation delay is around 21nS.

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three-bit binary code at the Select inputs. Two complementary outputs provide both inverting and non-inverting buffer operation. A Strobe input is provided which, when at the high level, disables all data inputs and forces the Y output to the low state and the W output to the high state. The Select input buffers incorporate internal overlap features to ensure that select input changes do not cause invalid output transients. RoboticsBD