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74LS And 74HC Series IC
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74LS20 Dual Four input NAND in Pakistan
74LS20 Dual Four input NAND in Pakistan
₨68
74LS20 Dual Four Input NAND in Pakistan
Packing list:
- 1x 74LS20 Dual Four input NAND
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- 74LS And 74HC Series IC
74LS76 DUAL JK FLIP-FLOP IC in Pakistan
74LS76 comes with dual JK flip-flops. JK flip flops are widely used in daily electronics devices by many methods but the basic operation of the JK flip flop is to store a bit. JK flip flop allows it to store a bit and then allows it to use for further functions. in digital electronics circuits. JK flip flop is one of the popular flip flops due to its clock input, pre-set, and clear functionalities. The JK flip-flop changes its state under the clock pulse signal. The clock signal can be either a positive edge or a negative edge. The clock pulse gives multiple advantages to the flip-flop. 74LS76 also has provided a feature to neglect or prevent invalid outputs.
SKU: D2025 - 74LS And 74HC Series IC
74LS32 74-LS32 74HC32 7432 Quad 2 Input OR Gate DIP IC SN74CH32N in Pakistan
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74LS And 74HC Series IC74LS32 74-LS32 74HC32 7432 Quad 2 Input OR Gate DIP IC SN74CH32N in Pakistan
This device contains four independent gates each of which performs the logic OR function. The 74LS32 is a 14-Pin Quad 2-Input OR Gate IC. The 74LS32 provides four independent 2-input OR gates with standard push-pull outputs. Featured by Sharvi Electronics The device is designed for operation with a power supply range of 2.0V to 6.0V. Inputs include clamp diodes. This enables the use of current-limiting resistors to interface inputs to voltages in excess of VCC.
SKU: D2000 - 74LS And 74HC Series IC
SMD 74HC595 74HC595D SOP16 Patch 8 Bit Serial Shift Register in Pakistan
Quick View74LS And 74HC Series ICSMD 74HC595 74HC595D SOP16 Patch 8 Bit Serial Shift Register in Pakistan
74HC595 8-bit Serial-to-Parallel Shift Register is a high-speed shift register that utilizes advanced silicon-gate CMOS technology. This device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads.
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register.
The shift register has direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register.
The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
SKU: D2013 - 74LS And 74HC Series IC
74HC165 Parallel To Serial 8 Bit Shift Register IC in Pakistan
The 74HC165 is a high-speed Si-gate CMOS device and is pin-compatible with low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the Ds input and shifts one place to the right (Q0 –> Q1 –> Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure that allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP is HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.
SKU: D2016
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