74LS20 Dual Four input NAND in Pakistan
74LS20 Dual Four input NAND in Pakistan
₨68
74LS20 Dual Four Input NAND in Pakistan
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- 1x 74LS20 Dual Four input NAND
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74HC595 8-bit Serial-to-Parallel Shift Register is a high-speed shift register that utilizes advanced silicon-gate CMOS technology. This device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads.
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register.
The shift register has direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register.
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This device contains four independent gates each of which performs the logic OR function. The 74LS32 is a 14-Pin Quad 2-Input OR Gate IC. The 74LS32 provides four independent 2-input OR gates with standard push-pull outputs. Featured by Sharvi Electronics The device is designed for operation with a power supply range of 2.0V to 6.0V. Inputs include clamp diodes. This enables the use of current-limiting resistors to interface inputs to voltages in excess of VCC.
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This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three-bit binary code at the Select inputs. Two complementary outputs provide both inverting and non-inverting buffer operation. A Strobe input is provided which, when at the high level, disables all data inputs and forces the Y output to the low state and the W output to the high state. The Select input buffers incorporate internal overlap features to ensure that select input changes do not cause invalid output transients. RoboticsBD
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Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).
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