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Electronic Devices And Components
Showing 461–480 of 1006 results
- 74LS And 74HC Series IC
7447 74HC47 74LS47 BCD to 7 Segment Decoder Driver DIP 16 in Pakistan
Quick View74LS And 74HC Series IC7447 74HC47 74LS47 BCD to 7 Segment Decoder Driver DIP 16 in Pakistan
74LS47 accepts four lines of BCD (8421) input data, generates their complements internally and decodes the data with seven AND/OR gates having open-collector outputs to drive indicator segments directly. Each segment output is guaranteed to sink 24 mA in the ON (LOW) state and withstand 15V in the OFF (HIGH) state with a maximum leakage current of 250 µA. Auxiliary inputs provided blanking, 74LS47 BCD to 7-Segment Decoder/Driver IC.
SKU: D2008 - 74LS And 74HC Series IC
7448 BCD To 7 Segment Decoder Driver IC 74LS48 SN74LS48N 74HC48 in Pakistan
Quick View74LS And 74HC Series IC7448 BCD To 7 Segment Decoder Driver IC 74LS48 SN74LS48N 74HC48 in Pakistan
The 74LS48 features active-high outputs for driving lamp buffers or common-cathode LEDs. They have full ripple-blanking input/output controls and a lamp test input. Display patterns for BCD input count above 9 are unique symbols to authenticate input conditions. Their circuits incorporate automatic leading and/or trailing-edge zero-blanking control (RBI\ and RBO\). Lamp test (LT\) of these types may be performed at any time when the BI\/RBO\ node is at a high level. They contain an overriding blanking input (BI\), which can be used to control the lamp intensity by pulsing or to inhibit the outputs. Inputs and outputs are entirely compatible for use with TTL logic outputs.
SKU: D2010 - 74LS And 74HC Series IC
7490 74LS90 IC Decade Counter in Pakistan
Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).
SKU: D2012 - 74LS And 74HC Series IC
74hc138 IC in Pakistan
The 74HC138 is a high-speed CMOS device. The device accepts a three-bit binary weighted address on input pins A0, A1, and A2 and when enabled will produce one active low output with the remaining seven being high. There are two active LOW enable inputs E1 and E2, and one active HIGH enable input E3. The disabled device state results in all outputs being high. The enable state occurs with E1 and E2 asserted low and E3 asserted high. The multiple enable lines to allow for the parallel expansion of decoders to create 4-to-16 line versions with no additional parts and 5-to-32 versions with the addition of a single inverter.
SKU: D2027 - 74LS And 74HC Series IC
74hc147 IC in Pakistan
The 74HC/HCT147 are high-speed Si-gate CMOS devices and are pin compatible with low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT147 9-input priority encoders accept data from nine active LOW inputs (A0 to A8) and provide a binary representation on the four active LOW outputs (Y0 to Y3). A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line A8 having the highest priority. The devices provide the 10-line to 4-line priority encoding function by use of the implied decimal “zero”. The “zero” is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH.
SKU: D2032 - 74LS And 74HC Series IC
74hc151 IC in Pakistan
74HC151 is 8 – Input Multiplexer 16 Pin IC. Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three binary code at select inputs. Two complementary outputs provide both inverting and non-inverting buffer operation. A Strobe input is provided which, when at a high level, disables all data inputs and forces Y output to low state and W output to a high state. Select input buffers incorporate internal overlap features to ensure that select input changes do not cause invalid output transients. Used for Boolean Function Generator.
SKU: D2031 - 74LS And 74HC Series IC
74HC157 Quad 2×1 Multiplexer MUX DIP IC SN74LS157N 74157 74-LS157 in Pakistan
Quick View74LS And 74HC Series IC74HC157 Quad 2×1 Multiplexer MUX DIP IC SN74LS157N 74157 74-LS157 in Pakistan
74HC157 is a high-speed multiplexer integrated circuit consisting of four 2-input digital multiplexers inside the chip. It is pin-compatible with Low-power Schottky TTL. It has two control inputs namely enable and select input. Additionally, it has two groups of registers. The selected input determines the register from which the data comes. Its operation is specified over a temperature range of -55 °C to 125 °C.
SKU: D2001 - 74LS And 74HC Series IC
74HC161 IC Presettable synchronous 4 bit binary counter Asynchronous reset in Pakistan
Quick View74LS And 74HC Series IC74HC161 IC Presettable synchronous 4 bit binary counter Asynchronous reset in Pakistan
he 74HC161 is a synchronous presettable binary counter with an internal look-ahead carry.
Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW.
A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset
takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET, and CEP
(thus providing an asynchronous clear function).The look-ahead carry simplifies the serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time.
Inputs include clamp diodes. This enables the use of current-limiting resistors to interface inputs to voltages in excess of VCC.SKU: D2058 - 74LS And 74HC Series IC
74hc164 IC in Pakistan
The 74HC164/ 74HCT164 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), and eight parallel data outputs (Q0 to Q7).
Data is entered serially through DSA or DSB and either input can be used as an active HIGH to enable data entry through the other input. Data is shifted on the LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the register and forces all outputs LOW, independently of other inputs. Inputs include clamp diodes. This enables the use of current-limiting resistors to interface inputs to voltages in excess of VCC.SKU: D2033 - 74LS And 74HC Series IC
74HC165 Parallel To Serial 8 Bit Shift Register IC in Pakistan
The 74HC165 is a high-speed Si-gate CMOS device and is pin-compatible with low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the Ds input and shifts one place to the right (Q0 –> Q1 –> Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure that allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP is HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.
SKU: D2016 - Logic Gate ICs
74HC595 74HC595D SMD IC SOP16 Patch 8 Bit Serial Shift Register In Pakistan
74HC595 SMD 8-bit serial-to-parallel Shift Register is a high-speed shift register that utilizes advanced silicon-gate CMOS technology. This device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and the ground.
SKU: D299 - 74LS And 74HC Series IC
74HC595N 8 Bit Serial To Parallel Shift Register IC in Pakistan
The 74HC595 is a high-speed shift register that utilizes advanced silicon-gate CMOS technology. 74HC595 device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register.
The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register of 74HC595 use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. See more information in the datasheet of 74HC595.
SKU: D2059