74hc138 IC in Pakistan
The 74HC138 is a high-speed CMOS device. The device accepts a three-bit binary weighted address on input pins A0, A1, and A2 and when enabled will produce one active low output with the remaining seven being high. There are two active LOW enable inputs E1 and E2, and one active HIGH enable input E3. The disabled device state results in all outputs being high. The enable state occurs with E1 and E2 asserted low and E3 asserted high. The multiple enable lines to allow for the parallel expansion of decoders to create 4-to-16 line versions with no additional parts and 5-to-32 versions with the addition of a single inverter.
₨145
The 74HC138 is a high-speed CMOS device. The device accepts a three-bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaining seven being high. There are two active LOW enable inputs E1 and E2, and one active HIGH enable input E3. The disabled device state results in all outputs being high. The enable state occurs with E1 and E2 asserted low and E3 asserted high. The multiple enable lines to allow for the parallel expansion of decoders to create 4-to-16 line versions with no additional parts and 5-to-32 versions with the addition of a single inverter.
Features:
- Wide Supply Voltage Range from 2.0V to 6.0V
- Sinks or sources 8 mA at VCC = 4.5V
- CMOS low power consumption
- Schmitt Trigger Action at All Inputs
- Inputs Accept up to 6.0V
- ESD Protection Tested per JESD 22
- Exceeds 200-V Machine Model (A115-A)
- Exceeds 2000-V Human Body Model (A114-A)
- Exceeds 1000-V Charged-Device Model (C101C)
- Latch-Up Exceeds 100mA per JESD 78D, Class II
Package Includes:
- 1 x 74hc138 IC in Pakistan
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SN74HC163N 74HC163 4-Bit Synchronous Binary Counters IC in Pakistan
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74LS And 74HC Series ICSN74HC163N 74HC163 4-Bit Synchronous Binary Counters IC in Pakistan
The SN74HC163 are synchronous, presettable counters that feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
SKU: D2023 - 74LS And 74HC Series IC
74HC165 Parallel To Serial 8 Bit Shift Register IC in Pakistan
The 74HC165 is a high-speed Si-gate CMOS device and is pin-compatible with low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the Ds input and shifts one place to the right (Q0 –> Q1 –> Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure that allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP is HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.
SKU: D2016
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