74LS139 Dual 1-of-4 Decoder/ Demultiplexer in Pakistan

These full adders perform the addition of two 4-bit binary
numbers. The sum (R) outputs are provided for each bit and
the resultant carry (C4) is obtained from the fourth bit.
These adders feature a full internal look ahead across all four
bits. This provides the system designer with a partial lookahead
performance at the economy and reduced package
count of a ripple-carry implementation.

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three-bit binary code at the Select inputs. Two complementary outputs provide both inverting and non-inverting buffer operation. A Strobe input is provided which, when at the high level, disables all data inputs and forces the Y output to the low state and the W output to the high state. The Select input buffers incorporate internal overlap features to ensure that select input changes do not cause invalid output transients. RoboticsBD

Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).