7475 74LS75 4-BIT BISTABLE LATCHES in Pakistan

Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).

The 74LS160 IC package, consisting of 16 pins, contains a single 4 bit synchronous counter circuit which can be wired for decade counting mod, without external logic chips. By wiring more than one 74LS160 together (cascading), it is possible to make higher count lengths (powers of ten). For example, two 74LS160s cascaded together would yield a counter capable of decimally counting the range 00 – 99.

The 74LS189 is a high-speed 64-bit RAM organized as a 16-word by the 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs are 3-state and are in the high impedance state whenever the Chip Select (CS) input is HIGH. The outputs are active only in the read mode and the output data is the complement of the stored data.