7473 FLIP FLOP JK in Pakistan

These are high-speed silicon-gate CMOS decoders well suited to memory address decoding or data-routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low-power Schottky TTL logic. Both circuits have three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC/HCT138 series goes low or which of the normally low outputs of the HC/HCT238 series go high. Two active low and one active high enables (E1, E2, and E3)are provided to ease the cascading of decoders. The decoder’s eight outputs can drive ten low-power Schottky TTL equivalent loads.

The 74LS138 is a 3:8 Decoder IC that is commonly used in decoding or de-multiplexing circuits for memory decoding or data routing purposes. It is designed for high-speed operations and has three enable pins to make it easier to cascade with other ICs. The device decodes 1-of-8 lines, set by x3 binary select inputs & three enable inputs. The LS138 can be used as an 8- output demultiplexer by using one active LOW Enable input as data input & the other Enable inputs as strobes. The IC has an operating voltage from 1.0V to 5.5V with a low power consumption of 32mW. The propagation delay is around 21nS.

These full adders perform the addition of two 4-bit binary
numbers. The sum (R) outputs are provided for each bit and
the resultant carry (C4) is obtained from the fourth bit.
These adders feature a full internal look ahead across all four
bits. This provides the system designer with a partial lookahead
performance at the economy and reduced package
count of a ripple-carry implementation.