7409 Quad Two input AND, Open collector in Pakistan
7409 Quad Two input AND, Open collector in Pakistan
₨69
7409 Quad Two input AND, Open collector in Pakistan
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- 1x 7409 Quad Two input AND, Open collector
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74LS And 74HC Series IC7448 BCD To 7 Segment Decoder Driver IC 74LS48 SN74LS48N 74HC48 in Pakistan
The 74LS48 features active-high outputs for driving lamp buffers or common-cathode LEDs. They have full ripple-blanking input/output controls and a lamp test input. Display patterns for BCD input count above 9 are unique symbols to authenticate input conditions. Their circuits incorporate automatic leading and/or trailing-edge zero-blanking control (RBI\ and RBO\). Lamp test (LT\) of these types may be performed at any time when the BI\/RBO\ node is at a high level. They contain an overriding blanking input (BI\), which can be used to control the lamp intensity by pulsing or to inhibit the outputs. Inputs and outputs are entirely compatible for use with TTL logic outputs.
SKU: D2010 - 74LS And 74HC Series IC
74LS148 3-Bit Priority Encoder IC (74148 IC) DIP-16 in Pakistan
74LS Series ICs are High-Speed Logic gates, ideally a little faster than the 74HC series but more power consumption is required. They are implemented with a Low-Power Schottky diode technology to achieve high switching speed. 74LS148 is one of the 74LS series IC. 74LS148 ICs contain an 8 to 3-Bit priority encoder that converts 8 Data Lines to 3-Line binary. Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry.
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74LS283 in Pakistan
These full adders perform the addition of two 4-bit binary
numbers. The sum (R) outputs are provided for each bit and
the resultant carry (C4) is obtained from the fourth bit.
These adders feature a full internal look ahead across all four
bits. This provides the system designer with a partial lookahead
performance at the economy and reduced package
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7490 74LS90 IC Decade Counter in Pakistan
Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).
SKU: D2012
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