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T74LS05B1 T74LS 05B1 S05B1 AND Gate IC in Pakistan
T74LS05B1 T74LS 05B1 S05B1 AND Gate IC in Pakistan
T74LS05B1 T74LS 05B1 S05B1 AND Gate IC in Pakistan
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- 1x T74LS05B1 T74LS 05B1 S05B1 AND Gate IC
Related products
- 74LS And 74HC Series IC
74HC157 Quad 2×1 Multiplexer MUX DIP IC SN74LS157N 74157 74-LS157 in Pakistan
Quick View74LS And 74HC Series IC74HC157 Quad 2×1 Multiplexer MUX DIP IC SN74LS157N 74157 74-LS157 in Pakistan
0 out of 5(0)74HC157 is a high-speed multiplexer integrated circuit consisting of four 2-input digital multiplexers inside the chip. It is pin-compatible with Low-power Schottky TTL. It has two control inputs namely enable and select input. Additionally, it has two groups of registers. The selected input determines the register from which the data comes. Its operation is specified over a temperature range of -55 °C to 125 °C.
SKU: D2001 - 74LS And 74HC Series IC
74LS283 in Pakistan
0 out of 5(0)These full adders perform the addition of two 4-bit binary
numbers. The sum (R) outputs are provided for each bit and
the resultant carry (C4) is obtained from the fourth bit.
These adders feature a full internal look ahead across all four
bits. This provides the system designer with a partial lookahead
performance at the economy and reduced package
count of a ripple-carry implementation.SKU: D2018 - 74LS And 74HC Series IC
IC 74LS85 4 Bit Magnitude Comparator DIP 16 in Pakistan
0 out of 5(0)74HC85 4-Bit Comparator IC (7485 IC) DIP-16 Package. 74LS85 is the four-bit magnitude comparators that perform a comparison of straight binary and straight BCD (8-4-2-1) codes. Three fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully expandable to any number of bits without external gates.
SKU: D2017 - 74LS And 74HC Series IC
74HC165 Parallel To Serial 8 Bit Shift Register IC in Pakistan
0 out of 5(0)The 74HC165 is a high-speed Si-gate CMOS device and is pin-compatible with low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the Ds input and shifts one place to the right (Q0 –> Q1 –> Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure that allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP is HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.
SKU: D2016
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