T74LS05B1 T74LS 05B1 S05B1 AND Gate IC in Pakistan

Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).

74LS76 comes with dual JK flip-flops. JK flip flops are widely used in daily electronics devices by many methods but the basic operation of the JK flip flop is to store a bit. JK flip flop allows it to store a bit and then allows it to use for further functions. in digital electronics circuits. JK flip flop is one of the popular flip flops due to its clock input, pre-set, and clear functionalities. The JK flip-flop changes its state under the clock pulse signal. The clock signal can be either a positive edge or a negative edge. The clock pulse gives multiple advantages to the flip-flop. 74LS76 also has provided a feature to neglect or prevent invalid outputs.

The 74HC165 is a high-speed Si-gate CMOS device and is pin-compatible with low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the Ds input and shifts one place to the right (Q0 –> Q1 –> Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure that allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP is HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.