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74LS And 74HC Series IC
74LS688 8-bit magnitude comparators in Pakistan
The SN54/74LS682, 684, and 688 are 8-bit magnitude comparators. These device types are designed to perform comparisons between two eight-bit binary or BCD words. All device types provide P = Q outputs and the LS682 and LS684 have P>Q outputs also. The LS682, LS684, and LS688 are totem pole devices. The LS682 has a 20 kΩ pullup resistor on the Q inputs for analog or switch data.
₨346
The SN54/74LS682, 684, and 688 are 8-bit magnitude comparators. These device types are designed to perform comparisons between two eight-bit binary or BCD words. All device types provide P = Q outputs and the LS682 and LS684 have P>Q outputs also. The LS682, LS684, and LS688 are totem pole devices. The LS682 has a 20 kΩ pullup resistor on the Q inputs for analog or switch data.
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- 74LS And 74HC Series IC
7447 74HC47 74LS47 BCD to 7 Segment Decoder Driver DIP 16 in Pakistan
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74LS And 74HC Series IC7447 74HC47 74LS47 BCD to 7 Segment Decoder Driver DIP 16 in Pakistan
74LS47 accepts four lines of BCD (8421) input data, generates their complements internally and decodes the data with seven AND/OR gates having open-collector outputs to drive indicator segments directly. Each segment output is guaranteed to sink 24 mA in the ON (LOW) state and withstand 15V in the OFF (HIGH) state with a maximum leakage current of 250 µA. Auxiliary inputs provided blanking, 74LS47 BCD to 7-Segment Decoder/Driver IC.
SKU: D2008 - 74LS And 74HC Series IC
7490 74LS90 IC Decade Counter in Pakistan
Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).
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74151 ic in Pakistan
This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three-bit binary code at the Select inputs. Two complementary outputs provide both inverting and non-inverting buffer operation. A Strobe input is provided which, when at the high level, disables all data inputs and forces the Y output to the low state and the W output to the high state. The Select input buffers incorporate internal overlap features to ensure that select input changes do not cause invalid output transients. RoboticsBD
SKU: D2022
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