74LS08 74AHS08 SN74LS08N LS08N 7408 QUAD 2-input AND Gate in Pakistan

The 74HC165 is a high-speed Si-gate CMOS device and is pin-compatible with low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the Ds input and shifts one place to the right (Q0 –> Q1 –> Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure that allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP is HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.

74LS02 74AHS02 7402 Quad 2-input NOR gate in Pakistan

The 74LS160 IC package, consisting of 16 pins, contains a single 4 bit synchronous counter circuit which can be wired for decade counting mod, without external logic chips. By wiring more than one 74LS160 together (cascading), it is possible to make higher count lengths (powers of ten). For example, two 74LS160s cascaded together would yield a counter capable of decimally counting the range 00 – 99.