7475 74LS75 4-BIT BISTABLE LATCHES in Pakistan

Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).

74LS Series ICs are High-Speed Logic gates, ideally a little faster than the 74HC series but more power consumption is required. They are implemented with a Low-Power Schottky diode technology to achieve high switching speed. 74LS148 is one of the 74LS series IC. 74LS148 ICs contain an 8 to 3-Bit priority encoder that converts 8 Data Lines to 3-Line binary. Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry.