7403 Quad Two input NAND, Open collector in Pakistan
7403 Quad Two input NAND, Open collector in Pakistan
7403 Quad Two input NAND, Open collector in Pakistan
Packing list:
- 1x 7403 Quad Two input NAND, Open collector
Related products
- 74LS And 74HC Series IC
74LS283 in Pakistan
0 out of 5(0)These full adders perform the addition of two 4-bit binary
numbers. The sum (R) outputs are provided for each bit and
the resultant carry (C4) is obtained from the fourth bit.
These adders feature a full internal look ahead across all four
bits. This provides the system designer with a partial lookahead
performance at the economy and reduced package
count of a ripple-carry implementation.SKU: D2018 - 74LS And 74HC Series IC
74LS32 74-LS32 74HC32 7432 Quad 2 Input OR Gate DIP IC SN74CH32N in Pakistan
Quick View74LS And 74HC Series IC74LS32 74-LS32 74HC32 7432 Quad 2 Input OR Gate DIP IC SN74CH32N in Pakistan
0 out of 5(0)This device contains four independent gates each of which performs the logic OR function. The 74LS32 is a 14-Pin Quad 2-Input OR Gate IC. The 74LS32 provides four independent 2-input OR gates with standard push-pull outputs. Featured by Sharvi Electronics The device is designed for operation with a power supply range of 2.0V to 6.0V. Inputs include clamp diodes. This enables the use of current-limiting resistors to interface inputs to voltages in excess of VCC.
SKU: D2000 - 74LS And 74HC Series IC
SN74HC163N 74HC163 4-Bit Synchronous Binary Counters IC in Pakistan
Quick View74LS And 74HC Series ICSN74HC163N 74HC163 4-Bit Synchronous Binary Counters IC in Pakistan
0 out of 5(0)The SN74HC163 are synchronous, presettable counters that feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
SKU: D2023
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